High speed signaling poses significant challenges with respect to signal loss between an IC operable within a high frequency range, and off-chip terminals, such as a dynamic random access memory (DRAM) interface, or an antenna for wireless applications. The cumulative path of a signal channel between the IC chip and off-chip signal origin/designation generally includes a package of the IC, and may further include an interposer on which the IC is affixed, and/or a circuit board on which the IC or interposer is affixed. Horizontal interconnect routing for a given communication channel in the IC package, and/or interposer, and/or board responsible for carrying such high speed signals may include a transmission line circuit for containing the electromagnetic wave as it is propagated. Such transmission lines are often in the form of a stripline, microstrip, or coplanar waveguide (CPW) circuit. Vertical interconnect routing for a given channel may include, for example, plated through holes and micro vias in a package substrate, socket pins/lands, and plated through holes in a motherboard.
Crosstalk between channels occurs when a signal transmitted on one channel of a transmission system creates an undesired effect in another channel and may be caused by one or more of capacitive, inductive, or conductive coupling between the channels. Interference between two channels as measured at an end of a path opposite from that of the transmitter is referred to as far end crosstalk (FEXT) and, assuming proper termination and non-interleave routing, is typically more problematic than near end crosstalk (NEXT) measured at the transmitter end of the path. Overall channel crosstalk, which is often predominantly FEXT, remains a problem in high data bandwidth applications (e.g., exceeding 2.0 Gbyte/sec), and can be the bandwidth limiter, particularly for single-ended channels.
Crosstalk from vertical transitions and horizontal microstrip routing are often both inductively dominant. As such, to maintain acceptable I/O performance, conventional I/O channel architectures may either employ conservative signal to ground (S:G) ratios in vertical transitions and/or stripline architectures in horizontal routing to mitigate crosstalk. Such techniques however disadvantageously increase pin count and layer count, respectively.